1. Field of Invention
The present invention relates to a semiconductor device and a connecting structure thereof. More particularly, the present invention relates to a chip package and a bump connecting structure thereof.
2. Description of Related Art
In the semiconductor industry, the production of integrated circuits (IC) is mainly divided into three phases: IC design, IC process, and IC package. In IC process, the chip is manufactured through wafer making, integrated circuit making, and wafer dicing etc. procedures. A wafer has an active surface, which refers generally to the surface on which the wafer has an active device. When the integrated circuit on the wafer has been made, the integrated circuit has a plurality of chip pads located on the active surface of the wafer. The chip eventually formed after wafer dicing may be electrically connected externally to a carrier through the chip pads. The carrier is, for example, a leadframe or a package substrate, and the chip may be connected to the carrier through wire bonding or flip chip bonding, so that the chip pads of the chip may be electrically connected to the contacts of the carrier.
In the flip chip bonding technology, after forming chip pads on the active surface of a wafer, bumps are formed on the chip pads respectively for electrically connecting the chip with the package substrate. Since these bumps are generally arranged on the active surface of the chip in area array, the flip chip bonding technology is suitable for chip packages with high contact number and high contact density, such that it has been widely used in the flip chip/ball grid array packages in the semiconductor industry. Moreover, compared with the wire bonding technology, the flip chip bonding technology may improve the electrical performance of the chip package because these bumps may provide shorter transmission paths between the chip and the carrier.
FIG. 1 is a cross-section view of a conventional flip chip package. Referring to FIG. 1, the conventional flip chip package 100 includes a chip 110, a substrate 120, a plurality of solder bumps 130, a plurality of under bump metallurgy (UBM) layers 140, and an underfill 150. The chip 110 has an active surface 112 and a plurality of chip pads 114 disposed on the active surface 112. In addition, the chip 110 further has a passivation layer 116 including a sub-passivation layer 116a and a stress buffer layer (SBL) 116b. The sub-passivation layer 116a and the stress buffer layer 116b overlay the active surface 112 to protect the chip 110 and expose each chip pad 114.
The UBM layers 140 are located between the chip pads 114 and the solder bumps 130 respectively. Each UBM layer 140 may include an adhesion layer, a barrier layer, and a wetting layer formed on the chip pad 114 sequentially. The UBM layers 140 are used for increasing the connecting strength between the solder bumps 130 and the chip pads 114, and for preventing the electro-migration.
The substrate 120 has a substrate surface 122, a plurality of bump pads 124, and a solder mask layer 126. The bump pads 124 are disposed on the substrate surface 122, and the solder mask layer 126 is disposed on the substrate surface 122 and exposes the bump pads 124. Each chip pad 114 is electrically connected to a corresponding bump pad 124 through one of the solder bumps 130. The material of the solder bumps 130 is, for example, lead solder or lead free solder.
The underfill 150 is located between the chip 110 and the substrate 120, and contains the solder bumps 130. The underfill 150 is used for protecting the solder bumps 130, and at the same time may reduce the thermal strain mismatch between the substrate 120 and the chip 110 when they are heated.
However, after the aforementioned flip chip package 100 has been used for a long time, cracks may appear on the side of the solder bumps 130 (especially solder bumps of lead-free solder) close to the chip pads 114, that results in the decrease of the reliability of the flip chip package 100. In addition, cracks may also appear on the side of the solder bumps 130 (especially solder bumps of lead-free solder) close to the bump pads 124, that results in the decrease of the reliability of the flip chip package 100.